The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing\nfoundry has raised security and privacy concerns with regard to intellectual property (IP) protection\nas well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious\nattacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely\nlogic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur\nconsiderable performance overhead upon the genuine IP design. The focus of this paper is to leverage\nthe unique property of emerging transistor technology on reducing the performance overhead as\nwell as preserving the robustness of logic locking technique. We design the polymorphic logic gate\nusing silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR\n(XOR)-based logic cone. We then evaluate the proposed technique based on security metric and\nperformance overhead.
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